The invention relates to an integrated circuit comprising a latch-up protection circuit in complementary MOS-circuitry technology wherein a substrate is provided having a substrate bias voltage terminal thereon which is connected to an output of a substrate bias voltage generator.
In integrated circuits of this type designed in complementary MOS-technology, the semiconductor substrate is not connected to the ground potential of the integrated circuit but is negatively charged by a substrate bias voltage generator. The substrate bias voltage of the substrate bias voltage generator reduces the transistor and junction capacitances and improves the switching speed. In the case of a semiconductor substrate composed of p-conducting material, which is provided with an inserted, n-conducting, well-like semiconductor zone, this is a negative substrate bias voltage of approximately -2 to -3 volts. The source zones of field effect transistors arranged on the semiconductor substrate outside the well-like semiconductor zone are connected to ground potential.
At the moment at which the positive supply voltage is switched on, the p-conducting semiconductor substrate in question first assumes a floating state in which it is cleared of external potentials.
This state is brought to an end by the actuation of the substrate bias voltage generator. The interval of time between the switching on of the supply voltage and the actuation of the substrate bias voltage generator is fundamentally influenced by the clock frequency, prevailing coupling capacitances, and the prevailing capacitive load. During the floating time, via the junction capacitances which exist on the one hand between the well-like semiconductor zone and the substrate, and on the other hand between those source zones connected to ground potential and the substrate, the semiconductor substrate can be temporarily charged to a positive bias voltage which does not disappear unil the substrate bias voltage generator is actuated, and which is replaced by the negative substrate bias voltage which gradually builds up at the output of the generator. However, also during the operation of the integrated circuits, more powerful currents which are shunted from the semiconductor substrate via the substrate bias voltage generator to a terminal of the latter which carries ground potential, can lead to a positive bias voltage of the semiconductor substrate as a result of the voltage drop across the internal resistance of the substrate bias voltage generator. Positive bias voltages represent a high security risk for the integrated circuit, however, since a latch-up effect can be triggered which generally results in the break-down of the integrated circuit.
In explaining the latch-up effect, let it be assumed that in general four consecutive semiconductor layers of alternating conductivity types are arranged between one terminal of the field-effect transistor of the first channel type, located in the well-like semiconductor zone, and one terminal of a field effect transistor of the second channel type located on the semiconductor substrate outside of this zone. The first terminal zone of the first-mentioned transistor forms the first semiconductor layer, the well-like semiconductor zone forms the second semiconductor layer, the semiconductor substrate forms the third semiconductor layer, and the first terminal zone of the last transistor forms the fourth semiconductor layer. This construction serves to form a parasitic, bipolar pnp-transistor and npn-transistor. The collector of the pnp-transistor corresponds to the base of the npn-transistor, and the base of the pnp-transistor corresponds to the collector of the npn-transistor. This structure forms a pnpn four-layer diode as in the case of a thyristor. When the semiconductor substrate carries a positive bias voltage, the pn-junction between the third and fourth semiconductor layers can be biased in the conducting direction to such an extent that between the aforesaid transistor terminals a current path is formed which can be traced to a parasitic thyristor effect within this four-layer structure. The current path remains even after the reduction of the positive substrate bias voltage and can thermally overload the integrated circuit.
In order to reduce the transistor and junction capacitances, it is known to use a negative substrate bias voltage in NMOS-technology, which is generated via a so-called substrate bias voltage generator on the integrated circuit (see the Semiconductor Electronics Series 14, "Integrated MOS-circuits" by H. Weiss and K. Horninger, page 247-248). The latchup effect in the case of positive semiconductor substrate voltages is likewise described on pages 111-112 of this book. Modification of the technology (doping profiles) or design techniques (trough spacings) are proposed as possible remedies. Another proposal to suppress the latch-up effect is described in the publication by D. Takacs et al, "Static and Transient Latch-up Hardness in N-Well CMOS With On-Chip Substrate Bias Generator", IEDM 85, Technical Digest, pages 504 to 508. There it is proposed to provide a clamping circuit which prevents a latch-up effect by limiting the semiconductor substrate potential to a value which is insufficient to activate the parasitic bipolar transistors in the semiconductor substrate. For this purpose, the clamping circuit shunts the high capacitive charge currents to ground.
Fundamentally, the above-described clamping circuit does not rule out the possibility of positive charging on the semiconductor substrate but merely compensates the effects thereof, since if a positive charging of the semiconductor substrate has occurred, a low-ohmic ground connection dissipates positive charge.